Semiconductor device with covering member that partially covers wiring substrate

ABSTRACT

An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation application of U.S. application Ser.No. 14/447,181 filed Jul. 30, 2014, which claims priority under 35 USC§119 from Japanese Patent Application No. 2013-182363 filed on Sep. 3,2013 including the specification, drawings and abstract is incorporatedherein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device, for example, atechnique that can be applied to a semiconductor device in which asemiconductor chip is mounted on a main surface of a wiring substrate.

As one of methods for mounting a semiconductor chip on the wiringsubstrate, there is a flip-chip structure. In the flip-chip structure, asurface of a semiconductor chip on which an electrode pad is formed isfaced toward the wiring substrate side, and the semiconductor chip ismounted on the wiring substrate with the use of a terminal disposed onthe electrode pad. In the flip-chip structure, a lid may be provided forthe purpose of radiating heat from the semiconductor chip, or protectingthe semiconductor chip (for example, refer to Japanese Unexamined PatentApplication Publication No. 2012-54597).

Japanese Unexamined Patent Application Publication No. Hei5(1993)-275552 discloses that corners of an insulating base on which anelectronic component such as a piezoelectric vibrator is mounted arenotched.

SUMMARY

The present inventors have studied that, in order to downsize anelectronic device having the semiconductor device, electronic components(for example, a capacitive element or a resistive element) that havebeen mounted on a mother board up to now is mounted on a surface of thewiring substrate on which no semiconductor chip is mounted. In order toconduct this mounting, there is a need to retain a first surface side ofthe wiring substrate to a retention jig after the semiconductor chip anda covering member such as the lid have been arranged on the firstsurface of the wiring substrate. In this case, the covering member maybe abutted against the retention jig to indirectly determine a positionof the wiring substrate relative to the retention jig.

On the other hand, because the covering member is fixed to the wiringsubstrate with the use of an adhesion layer, the covering member may beinclined with respect to the first surface of the wiring substrate. Inthis case, the position of the wiring substrate relative to theretention jig has the potential to vary. When the position is varied, anerror is generated in the mounting position of the electronic componenton the wiring substrate. The other problems and novel features willbecome apparent from the description of the present specification andthe attached drawings.

According to an embodiment, a first semiconductor chip is mounted on amain surface of a wiring substrate. A lid covers the main surface of thewiring substrate, and the first semiconductor chip. An electroniccomponent is mounted on a rear surface of the wiring substrate. The mainsurface of the wiring substrate has uncovered regions that are notcovered with the lid at at least two corners that face each other.

According to the embodiment, after the semiconductor chip and thecovering member such as the lid have been arranged on the first surfaceof the wiring substrate, the uncovered regions of the wiring substratecan be retained by the retention jig in retaining the first surface sideof the wiring substrate to the retention jig. Therefore, a precision inthe position of the wiring substrate relative to the retention jig isenhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a configuration of a semiconductordevice according to an embodiment;

FIG. 2 is a cross-sectional view taken along a line A-A′ in FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a main surface of awiring substrate;

FIG. 4 is a diagram illustrating a first example of a rear surface ofthe semiconductor device;

FIG. 5 is a diagram illustrating a second example of the rear surface ofthe semiconductor device;

FIG. 6 is a diagram illustrating a distance between a terminal connectedto an electronic component and an electrode;

FIG. 7 is a cross-sectional view illustrating a configuration of a firstsemiconductor chip;

FIGS. 8A to 8C are cross-sectional views illustrating a method ofmanufacturing the semiconductor device;

FIGS. 9A and 9B are cross-sectional views illustrating the method ofmanufacturing the semiconductor device;

FIG. 10 is a plan view illustrating a configuration of a retention jig;

FIG. 11 is a cross-sectional view taken along a line B-B′ in FIG. 10;

FIG. 12 is a cross-sectional view taken along a line C-C′ in FIG. 10;

FIG. 13 is a diagram illustrating advantages obtained by the provisionof an uncovered region on the wiring substrate;

FIG. 14 is a diagram illustrating advantages obtained by the provisionof the uncovered region on the wiring substrate;

FIG. 15 is a plan view illustrating a configuration of a semiconductordevice according to a modification 1;

FIG. 16 is a plan view illustrating a state in which the lid is removedfrom the semiconductor device illustrated in FIG. 15;

FIG. 17 is a diagram illustrating a first example of a rear surface ofthe wiring substrate;

FIG. 18 is a diagram illustrating a second example of the rear surfaceof the wiring substrate;

FIG. 19 is a diagram illustrating a third example of the rear surface ofthe wiring substrate;

FIG. 20 is a plan view illustrating the retention jig;

FIG. 21 is a cross-sectional view taken along a line B-B′ in FIG. 20;

FIG. 22 is a cross-sectional view taken along a line C-C′ in FIG. 20;

FIG. 23 is a diagram illustrating a rear surface of a wiring substratein a semiconductor device according to a modification 2;

FIG. 24 is a diagram illustrating the modification of FIG. 23;

FIG. 25 is a diagram illustrating the modification of FIG. 23;

FIG. 26 is a diagram illustrating the modification of FIG. 23;

FIG. 27 is a diagram illustrating a method of manufacturing asemiconductor device according to a modification 3;

FIGS. 28A and 28B are diagrams illustrating the method of manufacturingthe semiconductor device according to the modification 3;

FIGS. 29A and 29B are diagrams illustrating the method of manufacturingthe semiconductor device according to the modification 3;

FIGS. 30A and 30B are diagrams illustrating the method of manufacturingthe semiconductor device according to the modification 3;

FIG. 31 is a top view of the semiconductor device;

FIG. 32 is a rear view of the semiconductor device illustrated in FIG.31;

FIG. 33 is a rear view illustrating a modification of the semiconductordevice;

FIG. 34 is a rear view illustrating the modification of thesemiconductor device;

FIG. 35 is a rear view illustrating the modification of thesemiconductor device; and

FIG. 36 is a cross-sectional view illustrating the modification of thesemiconductor device.

DETAILED DESCRIPTION

Hereinafter, embodiments will be described with reference to theaccompanying drawings. In all of the drawings, the same components aredenoted by identical symbols, and a description thereof will beappropriately omitted.

Embodiments

FIG. 1 is a plan view illustrating a configuration of a semiconductordevice SD according to an embodiment. FIG. 2 is a cross-sectional viewtaken along a line A-A′ in FIG. 1. In FIG. 2, for facilitatingvisualization of the drawings, the number of external connectionterminals SB and the number of electronic components ELP1 are reduced.

The semiconductor device SD according to this embodiment includes afirst semiconductor chip SC1, a wiring substrate ISUB, a lid LID(covering member), and the electronic components ELP1. A rear surfaceSFC4 of the first semiconductor chip SC1 is an opposite surface of amain surface SFC3 thereof. The wiring substrate ISUB is rectangular, andincludes a main surface SFC1 (second main surface) and a rear surfaceSFC2 (second rear surface). The first semiconductor chip SC1 is mountedon the main surface SFC1. The lid LID covers the main surface SFC1 ofthe wiring substrate ISUB, and the first semiconductor chip SC1. Theelectronic components ELP1 are mounted on the rear surface SFC2 of thewiring substrate ISUB. The main surface SFC1 of the wiring substrateISUB has uncovered regions LDO not covered with the lid LID at at leasttwo corners facing each other. In other words, at at least two cornersfacing each other in the main surface SFC1, widths of portions notcovered with the lid LID are wider than other portions of edges of themain surface SFC1. Hereinafter, the configuration will be described indetail.

As illustrated in FIG. 2, the first semiconductor chip SC1 is mounted onthe wiring substrate ISUB in a flip chip manner. The first semiconductorchip SC1 is configured by, for example, a logic chip, but may beconfigured by a memory chip, a chip in which a logic chip and a memorycircuit are mixed together, or a power chip that controls an electricpower.

A plurality of electrode pads EL (to be described later with referenceto FIG. 7) are formed on the main surface SFC3 of the firstsemiconductor chip SC1. The first semiconductor chip SC1 is mounted onthe main surface SFC1 in such a direction that the main surface SFC3faces the main surface SFC1 of the wiring substrate ISUB. The electrodepads EL are connected to terminals (not shown) formed on the mainsurface SFC1 of the wiring substrate ISUB through terminals BMP (forexample, solder bumps, or conductor columns such as Cu columns or Aucolumns). A space formed between the main surface SFC3 of the firstsemiconductor chip SC1 and the main surface SFC1 of the wiring substrateISUB is sealed by an underfill resin UFR1. A part of the underfill resinUFR1 creeps along sides of the first semiconductor chip SC1 to form afillet.

The rear surface SFC4 of the first semiconductor chip SC1 is fixed tothe lid LID through an adhesion layer. It is preferable that theadhesion layer is high in thermal conductivity.

The lid LID is formed by drawing a plate made of metal such as Cu. As aresult, the lid LID is shaped so that a center portion CNT that contactswith the first semiconductor chip SC1, and an edge EDG are connected toeach other through a slope portion SLP. The slope portion SLP is slopedto be closer to the wiring substrate ISUB as the slope portion SLP isfarther from the center portion CNT. An inclination angle of the slopeportion SLP to the center portion CNT may be nearly perpendicular. Theedge EDG of the lid LID comes in contact with a region of the wiringsubstrate ISUB which is located outside of the underfill resin UFR1. Atleast a part of the edge EDG of the lid LID is fixed to the wiringsubstrate ISUB through the adhesion layer.

As illustrated in FIG. 1, a planar shape of the lid LID is notched attwo corners of a rectangle which face each other. Four corners of thelid LID overlap with respective four corners of the wiring substrateISUB. The uncoated regions LDO of the wiring substrate ISUB arepositioned at portions of the lid LID in which the corners are notched.A width of the portions of the uncoated regions LDO which overlap withthe diagonal line of the wiring substrate ISUB is, for example, equal toor larger than 1 mm, and equal to or smaller than 6 mm.

The slope portion SLP of the lid LID is formed along an outline in whichfour corners of a rectangle are notched. In other words, the slopeportion SLP is formed along the respective sides of an octagon. In theoctagon, respective two sides that face each other are parallel to eachother, and four sides facing the four corners of the wiring substrateISUB are each shorter than four sides facing the four sides of thewiring substrate ISUB.

As illustrated in FIG. 2, the wiring substrate ISUB is formed of, forexample, a resin interposer, and has a plurality of electrodes LND(first rear electrodes) on the rear surface SFC2. The plurality ofelectrodes LND are connected to the terminals BMP through through-holes(not shown) or lines (not shown) within the wiring substrate ISUB. Apart of the plurality of electrodes LND may be connected to electroniccomponents ELP through lines within the wiring substrate ISUB. Theelectrodes LND are provided with the external connection terminals SB.The external connection terminals SB are configured by, for example,solder balls.

The electronic components ELP are mounted on the rear surface SFC2 ofthe wiring substrate ISUB. The electronic components ELP are configuredby, for example, discrete components such as a capacitor, a resistor, oran inductor, but may be configured by a chip configuring a circuit. Theelectronic components ELP are connected to terminals ELA disposed on therear surface SFC2.

Also, as illustrated in FIG. 1, the main surface SFC1 of the wiringsubstrate ISUB is provided with an alignment mark AMK1. The alignmentmark AMK1 is a pattern made of the same conductor (for example, Cu) asthat of lines formed on the main surface SFC1, and used as a positioningpattern when the first semiconductor chip SC1 and the lid LID aremounted on the main surface SFC1. The alignment mark AMK1 is located inany uncoated region LDO of the main surface SFC1.

FIG. 3 is a diagram illustrating a configuration of the main surfaceSFC1 of the wiring substrate ISUB. A plurality of electrodes FNG (secondelectrodes) are formed in a region where the first semiconductor chipSC1 is to be arranged on the main surface SFC1. The respectiveelectrodes FNG are connected to the electrode pads EL of the firstsemiconductor chip SC1 through the terminals BMP.

FIG. 4 is a diagram illustrating a first example of a rear surface ofthe semiconductor device SD. In the example illustrated in this drawing,the plurality of external connection terminals SB and the plurality ofelectrodes LND are arranged in a region of the rear surface SFC2 exceptfor a portion that overlaps with the first semiconductor chip SC1,two-dimensionally, in other words, on lattice points. A plurality of theelectronic components ELP1 are mounted on a portion of the rear surfaceSFC2 where the electrodes LND and the external connection terminals SBare not formed, that is, a portion that overlaps with the firstsemiconductor chip SC1. The electronic components ELP1 are connected tothe first semiconductor chip SC1 through the through-holes and the linesof the wiring substrate ISUB. With this arrangement, an inductance of aconnection route that connects the first semiconductor chip SC1 and theelectronic components ELP1 can be reduced. The electronic componentsELP1 are configured by, for example, power enhancement capacitors.

FIG. 5 is a diagram illustrating a second example of the rear surface ofthe semiconductor device SD. The example illustrated in this drawing isidentical with the example illustrated in FIG. 4 except for thefollowing configurations. First, the electrodes LND and the externalconnection terminals SB are also formed under a portion of the rearsurface SFC2 which overlaps with the first semiconductor chip SC1. Theelectronic components ELP1 are arranged in the vicinity of an edge ofthe first semiconductor chip SC1. With this arrangement, as comparedwith the example illustrated in FIG. 4, the number of externalconnection terminals SB can be increased. Also, an inductance of aconnection route that connects the first semiconductor chip SC1 and theelectronic components ELP1 can be suppressed.

In each of FIGS. 4 and 5, at least a part of the electrodes LND and theexternal connection terminals SB may be omitted. Also, at least a partof the electrodes LND of the rear surface SFC2 is used as a positioningmark when the electronic components ELP1 are mounted on the rear surfaceSFC2. The electrode LND is located, for example, at a corner of the rearsurface SFC2.

FIG. 6 is a diagram illustrating a distance between the terminals ELAconnected to the electronic components ELP and the electrodes LND. Theelectronic components ELP each have two terminals ELB. In correspondencewith those terminals ELB, two terminals ELA are formed on the rearsurface SFC2 for one electronic component ELP. It is assumed that adistance between a center of one terminal ELA and a center of theelectrodes LND aligned in a first direction (X-direction in the figure)is LB_(BC), and a distance between a center of the other terminal ELAand a center of the electrodes LND aligned in a second direction(Y-direction in the figure) is LA_(BC). Also, it is assumed that aradius of the electrodes LND is r, a half width of the terminals ELA inthe first direction (X-direction in the figure) is B_(p), and a halfwidth of the terminals ELA in the second direction (Y-direction in thefigure) is A_(p). Also, it is assumed that a half width of the terminalsELB in the first direction (X-direction in the figure) is B_(c), and ahalf width of the terminals ELB in the second direction (Y-direction inthe figure) is A_(c). Also, it is assumed that an interval between thetwo terminals ELA is G. Then, Expression (1), (2), or (3) describedbelow is satisfied. Any one of Expressions (2) and (3) larger on a rightside is selected.

LA _(BC) >r+A _(c) +A _(p)  (1)

LB _(BC) >r+B _(c) +B _(p)  (2)

LB _(BC) >r+G+B _(p)  (3)

In the example illustrated in FIG. 6, the electronic components ELPinclude two kinds of electronic components ELP1 and ELP2. The planarshapes of the electronic components ELP1 and ELP2 are each rectangular.The terminals ELB of the electronic components ELP1 are formed along thetwo long sides of the rectangle, and the terminals ELB of the electroniccomponents ELP2 are formed along the two short sides of the rectangle.

FIG. 7 is a cross-sectional view illustrating a configuration of thefirst semiconductor chip SC1. The first semiconductor chip SC1 has aconfiguration in which a multilayer wiring layer MINC is stacked on asubstrate SUB. The substrate SUB is formed of, for example, a siliconsubstrate. A plurality of semiconductor elements, for example,transistors are formed on the substrate SUB. The electrode pads EL areformed on an uppermost wiring layer of the multilayer wiring layer MINC.The electrode pads EL are connected to the electrodes FNG of the wiringsubstrate ISUB illustrated in FIG. 3 through the terminals BMPillustrated in FIG. 2.

FIGS. 8A to 8C and 9A, 9B are cross-sectional views illustrating amethod of manufacturing the semiconductor device SD. Before thoseprocesses illustrated in those drawings, the first semiconductor chipSC1 is prepared. The first semiconductor chip SC1 is formed, forexample, as follows.

First, an element isolation film is formed on the substrate SUB. Anelement formation region is isolated by the element isolation film. Theelement isolation film is formed through, for example, an STI technique,but may be formed through a LOCOS technique. Then, a gate insulatingfilm and a gate electrode are formed on the substrate SUB located in theelement formation region. The gate insulating film may be formed of asilicon oxide film, or may be formed of a high dielectric constant film(for example, hafnium silicon film) higher in dielectric constant thanthe silicon oxide film. When the gate insulating film is formed of thesilicon oxide film, the gate electrode is formed of a polysilicon film.Also, when the gate insulating film is a high dielectric constant film,the gate electrode is formed of a laminated film of a metal film (forexample, TiN) and a polysilicon film. Also, when the gate electrode ismade of polysilicon, a polysilicon resistor may be formed on the elementisolation film in a process of forming the gate electrode.

Subsequently, extension regions of the source and the drain are formedon the substrate SUB located in the element formation region. Then, asidewall is formed on a side wall of the gate electrode. Then, impurityregions that form the source and the drain are formed on the substrateSUB located in the element formation region. In this way, a MOStransistor is formed on the substrate SUB.

Then, the multilayer wiring layer MINC is formed on the elementisolation film and the MOS transistor. The electrode pads EL are formedon the uppermost wiring layer. Then, a protective insulating film(passivation film) is formed on the multilayer wiring layer MINC.Openings located on the EL are formed in the protective insulating film.Then, the terminals BMP are formed on the electrode pads EL.

Then, as illustrated in FIG. 8A, the first semiconductor chip SC1 ismounted on the main surface SFC1 of the wiring substrate ISUB. Then, asillustrated in FIG. 8B, the underfill resin UFR1 is allowed to flow intoa space formed between the main surface SFC1 and the first semiconductorchip SC1. The underfill resin UFR1 may be formed of an NCF(nonconductive film). In this case, the NCF is formed on the mainsurface SFC1 before the first semiconductor chip SC1 is mounted on themain surface SFC1.

Then, as illustrated in FIG. 8C, the lid LID is fixed onto the rearsurface SFC4 of the first semiconductor chip SC1 and the main surfaceSFC1 of the wiring substrate ISUB.

In the processes illustrated in FIGS. 8A to 8C, the alignment mark AMK1is used to determine the orientations of the first semiconductor chipSC1 and the lid LID relative to the wiring substrate ISUB. Thepositioning of the first semiconductor chip SC1 and the lid LID relativeto the wiring substrate ISUB is conducted on the basis of anotheralignment mark formed on the main surface SFC1 of the wiring substrateIS UB.

Then, as illustrated in FIG. 9A, the rear surface SFC2 of the wiringsubstrate ISUB is turned upward. Then, the electronic components ELP aremounted on the rear surface SFC2. Thereafter, as illustrated in FIG. 9B,the external connection terminals SB are mounted on the electrodes LNDof the rear surface SFC2.

FIG. 10 is a plan view illustrating a configuration of a retention jigHLD used when the electronic components ELP and the external connectionterminals SB are mounted on the rear surface SFC2. FIG. 11 is across-sectional view taken along a line B-B′ in FIG. 10, and FIG. 12 isa cross-sectional view taken along a line C-C′ of FIG. 10.

The retention jig HLD is formed of a plate member, and has an opening OPin a center portion thereof. A planar shape of the opening OP issubstantially rectangular, and substantially identical in size with theplanar shape of the wiring substrate ISUB. That is, the wiring substrateISUB is fitted into the opening OP. Two corners facing each other infour corners of the opening OP are each formed with a support portionPRJ. Each of the support portions PRJ is shaped to project from an innersurface of the opening OP toward an inside of the opening OP. A surfaceof the support portion PRJ on which the wiring substrate ISUB is fittedis lower in height than a main body of the retention jig HLD. In theexample illustrated in this figure, the support portions PRJ are eachformed along two side surfaces configuring the corner of the opening OP.

Then, the wiring substrate ISUB to which the first semiconductor chipSC1 and the lid LID have been attached is fitted into the retention jigHLD in such a direction that the main surface SFC1 faces the retentionjig HLD. In this situation, the uncovered regions LDO of the wiringsubstrate ISUB are configured to face the support portions PRJ. With theabove configuration, upper surfaces of the support portions PRJ areabutted against the uncovered regions LDO of the wiring substrate ISUB,and positioned by the support portions PRJ of the wiring substrate ISUB.

Subsequently, the advantages obtained by the provision of the uncoveredregions LDO on the wiring substrate ISUB will be described using FIGS.13 and 14.

The lid LID is fixed to the wiring substrate ISUB with the use of anadhesion layer ADA, but a thickness of the adhesion layer ADA is likelyto be varied. For that reason, the lid LID may be inclined with respectto the wiring substrate ISUB.

If the uncovered regions LDO are not provided on the wiring substrateISUB, a substantially overall surface of the wiring substrate ISUB iscovered with the lid LID. For that reason, as illustrated in FIG. 13,the support portions PRJ of the retention jig HLD support the edge EDGof the lid LID. In this example, when the lid LID is inclined withrespect to the substrate SUB, the rear surface SFC2 is also included ina state where the wiring substrate ISUB is held by the retention jigHLD.

When the rear surface SFC2 is inclined, there is a concern that theelectrode LND located adjacent to the electrode LND to be used as thealignment mark is falsely recognized as the alignment mark. In thiscase, there is a concern that the electronic components ELP are mountedon an incorrect place.

Also, when a flux is coated on the wiring substrate ISUB through ascreen printing technique before the external connection terminals SBare formed thereon, if the rear surface SFC2 is inclined, the screenmask may be deformed, or the amount of coating of flux may becomeuneven.

On the contrary, in this embodiment, as illustrated in FIG. 14, becausethe upper surfaces of the support portions PRJ of the retention jig HLDare abutted against the uncovered regions LDO of the wiring substrateISUB, the wiring substrate ISUB are positioned by the support portionsPRJ. Therefore, even if the lid LID is inclined with respect to thewiring substrate ISUB, the rear surface SFC2 of the wiring substrateISUB is situated at a given angle (for example, parallel) to theretention jig HLD. Therefore, the drawbacks described with reference toFIG. 13 are difficult to generate.

Modification 1

FIG. 15 is a plan view illustrating a configuration of a semiconductordevice SD according to a modification 1. FIG. 16 is a plan viewillustrating a state in which the lid is removed from the semiconductordevice SD illustrated in FIG. 15. The semiconductor device according tothis modification has the same configuration as that of thesemiconductor device SD according to the embodiment except for thefollowing configurations.

First, as illustrated in FIG. 15, all of the four corners of the lid LIDare notched. The uncovered regions LDO are disposed for all of the fourcorners of the wiring substrate ISUB.

Also, as illustrated in FIG. 16, the first semiconductor chip SC1 aswell as a second semiconductor chip SC2 is mounted on the main surfaceSFC1 of the wiring substrate ISUB. The second semiconductor chip SC2 hasthe same configuration as that of the first semiconductor chip SC1illustrated in FIG. 8. Also, the electrode FNG (fourth electrode) forconnection to the electrode pads EL (third electrodes) of the secondsemiconductor chip SC2 is formed in a region of the wiring substrateISUB which faces the second semiconductor chip SC2. The secondsemiconductor chip SC2 is mounted on the main surface SFC1 in theflip-chip manner as with the first semiconductor chip SC1. A surface(fifth main surface) of the second semiconductor chip SC2 on which theelectrode pads EL are formed is sealed by an underfill resin UFR2.

In the modification, the first semiconductor chip SC1 and the secondsemiconductor chip SC2 are each rectangular, and mounted on the mainsurface SFC1 in such a direction that the respective long sides areparallel to each other. For that reason, a stress is liable to beexerted on the wiring substrate ISUB in a direction warping in adirection (Y-direction in the figure) along the long sides of the firstsemiconductor chip SC1. In the example illustrated in the figure, theshort sides of the first semiconductor chip SC1 are parallel to a thirdside SID3 and a fourth side SID4 of the wiring substrate ISUB, and thelong sides of the first semiconductor chip SC1 are parallel to a firstside SID1 and a second side SID2 of the wiring substrate ISUB.

On the contrary, in this modification, as illustrated in FIG. 15, widthsof edges EDG1 and EDG2 which are regions parallel to the short sides ofthe first semiconductor chip SC1 are wider than widths of edges EDG3 andEDG4 which are regions parallel to the long sides of the firstsemiconductor chip SC1. The edges EDG1 and EDG2 of the lid LID are fixedto the main surface SFC1. However, the edges EDG3 and EDG4 merely comein contact with the main surface SFC1. In other words, the lid LID isfixed along the first side SID1 and the second side SID2 of the wiringsubstrate ISUB. However, the lid LID is not fixed to the third side SID3and the fourth side SID4. With the above configuration, the warp of thewiring substrate ISUB can be suppressed by the lid LID.

FIG. 17 is a diagram illustrating a first example of the rear surfaceSFC2 of the wiring substrate ISUB in this modification. In the exampleillustrated in FIG. 17, the electronic components ELP are disposed in aregion of the rear surface SFC2 which overlaps with the firstsemiconductor chip SC1, and a region of the rear surface SFC2 whichoverlaps with the second semiconductor chip SC2. The electroniccomponents ELP located in the region that overlaps with the firstsemiconductor chip SC1 are electrically connected to the firstsemiconductor chip SC1. Also, the electronic components ELP located inthe region that overlaps with the second semiconductor chip SC2 areelectrically connected to the second semiconductor chip SC2.

FIG. 18 is a diagram illustrating a second example of the rear surfaceSFC2 of the wiring substrate ISUB in this modification. In the exampleillustrated in FIG. 18, the electronic components ELP are disposed atleast around a region of the rear surface SFC2 which overlaps with thefirst semiconductor chip SC1, and around a region of the rear surfaceSFC2 which overlaps with the second semiconductor chip SC2. In theexample illustrated in FIG. 18, the first semiconductor chip SC1 islarger than the second semiconductor chip SC2. The electronic componentsELP are disposed around a region of the rear surface SFC2 which overlapswith the first semiconductor chip SC1. Those electronic components ELPare electrically connected to the first semiconductor chip SC1.

FIG. 19 is a diagram illustrating a third example of the rear surfaceSFC2 of the wiring substrate ISUB in this modification. In the exampleillustrated in FIG. 19, the first semiconductor chip SC1 is larger thanthe second semiconductor chip SC2. The electronic components ELP aredisposed around a region of the rear surface SFC2 which overlaps withthe first semiconductor chip SC1, and in a region of the rear surfaceSFC2 which overlaps with the second semiconductor chip SC2. Theelectronic components ELP located around the region that overlaps withthe first semiconductor chip SC1 are electrically connected to the firstsemiconductor chip SC1. The electronic components ELP located in theregion that overlaps with the second semiconductor chip SC2 areelectrically connected to the second semiconductor chip SC2.

A method of manufacturing the semiconductor device SD according to thismodification is identical with the method of manufacturing thesemiconductor device SD according to the embodiment except for the shapeof the opening OP of the retention jig HLD.

FIG. 20 is a plan view illustrating a configuration of the retention jigHLD used in this modification. FIG. 21 is a cross-sectional view takenalong a line B-B′ in FIG. 20. FIG. 22 is a cross-sectional view takenalong a line C-C′ in FIG. 20. The retention jig HLD illustrated in thosefigures is identical in configuration with the retention jig HLD shownin the embodiment except that the support portions PRJ are formed at therespective four corners of the opening OP.

This modification also obtains the same advantages as those in theembodiment. Also, the respective uncovered regions LDO are formed at allof the four corners of the wiring substrate ISUB. Also, incorrespondence with this configuration, the respective support portionsPRJ are formed at all of the four corners of the opening OP of theretention jig HLD. Therefore, when the wiring substrate ISUB is fittedinto the opening OP, the wiring substrate ISUB can be prevented frommoving relative to the retention jig HLD.

Modification 2

FIG. 23 is a diagram illustrating a rear surface SFC2 of a wiringsubstrate ISUB in a semiconductor device SD according to a modification2. The semiconductor device according to this modification is identicalin configuration with the semiconductor device SD according to theembodiment except that at least one second rear electrode AMK2(conductor pattern) is provided on the rear surface SFC2.

The second rear electrode AMK2 is configured by a conductor pattern (forexample, a Cu pattern) in the same layer as that of the electrodes LND,and formed in the same process as that of the electrodes LND. However,the second rear electrode AMK2 is different in at least one of size andshape from the electrodes LND. The second rear electrode AMK2 is used asa positioning mark when the electronic components ELP are mounted on therear surface SFC2. In the example illustrated in FIG. 23, the secondrear electrodes AMK2 are arranged at the respective two corners facingeach other on the rear surface SFC2. In this case, the electrodes LNDare not formed in a region of the rear surface SFC2 closer to an edge ofthe rear surface SFC2 than the second rear electrodes AMK2.

The external connection terminals SB are not formed on the second rearelectrodes AMK2. With the above configuration, the shape and the size ofthe second rear electrodes AMK2 can be arbitrarily set. The externalconnection terminals SB may be formed on the second rear electrodesAMK2.

Also, as illustrated in FIG. 24, the second rear electrodes AMK2 may bearranged in regions of the rear surface SFC2 in which the electrodes LNDare formed. In the example illustrated in FIG. 24, the two second rearelectrodes AMK2 are arranged at positions facing each other across aregion of the rear surface SFC2 which overlaps with the firstsemiconductor chip SC1. In other words, the second rear electrodes AMK2are arranged at the positions facing each other across the plurality ofelectronic components ELP.

As illustrated in FIGS. 25 and 26, the second rear electrodes AMK2 maybe arranged in the semiconductor device SD according to the modification1.

In an example illustrated in FIG. 25, four second rear electrodes AMK2are disposed. Two of those second rear electrodes AMK2 are arranged atpositions facing each other across a region of the rear surface SFC2which overlaps with the first semiconductor chip SC1, and the tworemaining second rear electrodes AMK2 are arranged at positions facingeach other across a region of the rear surface SFC2 which overlaps withthe second semiconductor chip SC2.

In an example illustrated in FIG. 26, two second rear electrodes AMK2are disposed. A first second rear electrode AMK2 is arranged in thevicinity of a region of the rear surface SFC2 which overlaps with thefirst semiconductor chip SC1, and a second second rear electrode AMK2 isarranged in the vicinity of a region of the rear surface SFC2 whichoverlaps with the second semiconductor chip SC2.

This modification also obtains the same advantages as those in theembodiment. Also, aside from the electrodes LND, the second rearelectrodes AMK2 are disposed as the positioning mark. The second rearelectrodes AMK2 are different in at least one of planar shape and sizefrom the electrodes LND. For that reason, a possibility that theelectrodes LND are falsely recognized as the second rear electrodes AMK2becomes lower. Therefore, the position of the electronic components ELPcan be further prevented from being shifted when the electroniccomponents ELP are mounted on the rear surface SFC2 of the wiringsubstrate ISUB.

Modification 3

The semiconductor device SD according to this modification has a sealingresin MDR instead of the lid LID. Then, the first semiconductor chip SC1is mounted on the wiring substrate ISUB with the use of bonding wiresWIR.

FIGS. 27 to 30B are diagrams illustrating a method of manufacturing thesemiconductor device SD according to this modification. First, asillustrated in a plan view of FIG. 27, the wiring substrate ISUB isprepared. In a state illustrated in those figures, a plurality (forexample, 1×n) of wiring substrates ISUB are connected to each other.

Then, as illustrated in a plan view of FIG. 28A and a cross-sectionalview of FIG. 28B, the first semiconductor chip SC1 and the electroniccomponents ELP are mounted on each of the main surfaces SFC1 of theplurality of wiring substrates ISUB. The first semiconductor chip SC1 ismounted on the main surface SFC1 in such a direction that the rearsurface SFC4 faces the main surface SFC1 of the wiring substrate ISUB.Then, the electrode pads EL of the first semiconductor chip SC1 areconnected to the wiring substrate ISUB with the use of the bonding wiresWIR.

Then, as illustrated in a cross-sectional view of FIG. 29A, a mold MMDis arranged on the main surface SFC1 of the wiring substrate ISUB. Themold MMD has cavities in regions facing the respective wiring substratesISUB. Then, the sealing resin MDR is allowed to flow into each of theplurality of cavities. Thereafter, as illustrated in FIG. 29B, the moldMMD is removed. In this way, the plurality of first semiconductor chipsSC1 are sealed by the sealing resin MDR, individually. The electroniccomponents ELP on the main surface SFC1 are also sealed by the sealingresin MDR. In this example, at least a part of the wiring substrate ISUBlocated on both ends thereof is not covered with the sealing resin MDR,and form with the uncovered regions LDO.

Thereafter, as illustrated in FIG. 30A, the electronic components ELPand the external connection terminals SB are mounted on the rear surfaceSFC2 in such a manner that the rear surface SFC2 of the wiring substrateISUB is turned upward. In this situation, like the embodiment, theretention jig HLD is used. The support portions PRJ of the retention jigHLD are abutted against regions (uncovered regions LDO) of the edges ofthe wiring substrate ISUB located on both ends thereof which are notcovered with the sealing resin MDR. For that reason, even if an uppersurface of the sealing resin MDR is inclined, the rear surface SFC2 ofthe wiring substrate ISUB can be prevented from being inclined withrespect to the retention jig HLD as in the embodiment.

Thereafter, as illustrated in FIG. 30B, the wiring substrate ISUB isdivided, and the semiconductor device SD is diced.

FIG. 31 is a top view of the semiconductor device SD according to thismodification. A shape of an upper surface of the sealing resin MDR issubstantially identical with the shape of the upper surface of the lidLID according to the modification 1 except that no edge EDG is provided.A part of the alignment mark AMK1 is sealed with the sealing resin MDR.

FIG. 32 is a rear view of the semiconductor device SD illustrated inFIG. 31. Also, in this modification, a plurality of external connectionterminals SB are disposed on the rear surface SFC2 of the wiringsubstrate ISUB. A plurality of electronic components ELP are mounted ina region of the rear surface SFC2 which overlaps with the firstsemiconductor chip SC1. Those electronic components ELP are electricallyconnected to the first semiconductor chip SC1.

As illustrated in FIG. 33, the second rear electrodes AMK2 shown in themodification 2 may be disposed on the rear surface SFC2 of the wiringsubstrate ISUB. In the example illustrated in FIG. 33, the second rearelectrodes AMK2 are disposed in a dicing region DSA.

Also, as illustrated in FIG. 34, in a state where the semiconductordevice SD has not yet been diced, n×m wiring substrates ISUB may beconnected to each other. In this case, as illustrated in FIG. 35, thesecond rear electrodes AMK2 may be disposed.

Also, as illustrated in FIG. 36, the mold MMD may be shaped to have onecavity. In this case, a plurality of first semiconductor chips SC1, anda plurality of electronic components ELP are located within the samecavity, and the first semiconductor chips SC1 and the electroniccomponents ELP are sealed by the sealing resin MDR in a lump. Also, inthis example, at least a part of the edges of the wiring substrate ISUBlocated on both ends thereof is not sealed by the sealing resin MDR.Therefore, the support portions PRJ of the retention jig HLD are abuttedagainst regions (uncovered regions LDO) of the edges of the wiringsubstrate ISUB located on both ends thereof which are not covered withthe sealing resin MDR. For that reason, the rear surface SFC2 of thewiring substrate ISUB can be prevented from being inclined with respectto the retention jig HLD.

The invention made by the present inventors has been described abovespecifically on the basis of the embodiments. However, the presentinvention is not limited to the embodiments, but can be variouslychanged without departing from the spirit of the invention.

What is claimed is:
 1. A semiconductor device, comprising: a substrateincluding a semiconductor chip; a covering member that covers a firstsurface of the substrate and the semiconductor chip, the covering memberincluding a first portion, a second portion and an third portion, thethird portion is mounted to the substrate and the second portionconnects the first portion to the third portion; and an electroniccomponent that is mounted on a second surface of the substrate, whereinthe first surface of the substrate includes a region that is not coveredby the covering member.
 2. The semiconductor device according to claim1, wherein the third portion extends in a first direction and the secondportion extends in a second direction that intersects with the firstdirection.
 3. The semiconductor device according to claim 2, wherein thefirst portion extends in the first direction.
 4. The semiconductordevice according to claim 2, wherein the third portion has a length inthe first direction that is less than a length of the first portion inthe first direction.
 5. The semiconductor device according to claim 2,wherein the third portion includes a first surface and a second surface,the first surface of the third portion is longer than the second surfaceof the third portion.
 6. The semiconductor device according to claim 5,wherein the first surface of the third portion is longer in the firstdirection than the second surface of the third portion in the firstdirection.
 7. The semiconductor device according to claim 2, wherein thefirst portion includes a first surface and a second surface, the firstsurface of the first portion is longer than the second surface of thefirst portion.
 8. The semiconductor device according to claim 7, whereinthe first surface of the first portion is longer in the first directionthan the second surface of the first portion in the first direction. 9.The semiconductor device according to claim 1, wherein the secondportion is sloped between the third portion and the first portion. 10.The semiconductor device according to claim 1, wherein the uncoveredregion is provided at an edge of the substrate.
 11. The semiconductordevice according to claim 1, wherein the uncovered region is provided ata corner the substrate.
 12. The semiconductor device according to claim1, wherein each corner of the substrate is not covered by the coveringmember.
 13. The semiconductor device according to claim 1, wherein thecovering member includes a notch that overlaps with a corner of thesubstrate.
 14. The semiconductor device according to claim 1, wherein awidth of a portion of the uncovered region that overlaps with a diagonalline of the wiring substrate is greater than or equal to 1 mm, and lessthan or equal to 6 mm.
 15. The semiconductor device according to claim1, wherein the covering member contacts the semiconductor chip.
 16. Thesemiconductor device according to claim 1, wherein the third portionincludes a plurality of sides at least two of which are fixed to thesubstrate.
 17. The semiconductor device according to claim 1, whereinthe third portion includes a plurality of sides, wherein at least one ofthe sides is fixed to the substrate and at least one of the sides is notfixed to the substrate.